Energy converting device

ABSTRACT

Device for reversible conversion of electric power capable of being connected between at least an input alternating voltage source and at least a load forming an output alternating current source, each input alternating voltage source having a supply terminal and a neutral terminal. The device comprises at least a switching block and includes an input terminal for connecting the supply terminal, a single reference terminal and an output terminal. Each switching block consists of a switching matrix formed of capacitors and switching cells, individually controlled. Each reference terminal is connected to a reference point other than the neutral terminal, and each block comprises elements for permanently maintaining at a constant or null sign the difference of potential between the first input terminal and the reference terminal.

The present invention relates to a device for reversibly convertingelectrical energy with chopping between one or more alternating voltagesources and one or more alternating current sources.

Existing solutions based on contactors or thyristors and transformersallow this type of conversion to be carried out.

However, these solutions allow only adjustment which is discrete andtherefore imprecise, and the response thereof is slow.

These solutions further require transformers having-intermediate taps inorder to carry out the adjustment of the voltage. The cost of theassembly is therefore high.

Other solutions for producing energy converting devices use associationsof capacitors and switches allowing the current to be commutated betweenthe various capacitors and the signal to be converted in this manner.

Such use of commutated capacitors for carrying out a conversion of asignal is a conventional technique of electronics.

A semi-conductor network acting as switches and capacitors arranged inthe form of a matrix between a voltage source and a current source isused in the device described in French patent application No. 00 06 786,filed on 26 May 2000, by the same applicant.

However, the device described in French patent application 00 06 786does not allow a conversion to be carried out between an alternatingvoltage source and an alternating current source.

A device which theoretically carries out a conversion between analternating voltage source and an alternating current source isdescribed in the article by D.-H. KWON, D.-D. MIN and J.-H.KIM, entitled“Novel topologies of AC choppers”, published in IEE Proceedings onElectr. Power Appl., pages 323-330, volume 143, No. 4, July 1996.

However, this article describes, in a purely theoretical manner, aspecific case having three alternating current sources and disregardspractical installation problems relating to electronic circuits ofaverage and high power.

In particular, it will be appreciated that the electronic circuits ofthis document pose excess-voltage risks which are high at low power andcritical at high power, in particular greater than 750 kW.

The object of the invention is to overcome this problem by allowingreversible conversion of electrical energy between one or morealternating voltage sources and one or more alternating current sources,which conversion is reliable for all power levels.

To this end, the invention relates to a device for reversibly convertingelectrical energy, which device can be connected between at least oneinput alternating voltage source and at least one load which forms anoutput alternating current source, each input alternating voltage sourcehaving a supply terminal and a neutral terminal, the device comprisingat least one commutation block which is suitable for being associatedwith an output alternating current source and which comprises an inputterminal, to which the supply terminal of the input alternating voltagesource can be connected, at least one reference terminal and an outputterminal, to which the load which forms the output alternating currentsource can be connected, the block also comprising a commutation matrixwhich is formed by capacitors and commutation cells, which cells arecontrolled individually by means for controlling the operation thereof,characterised in that the or each commutation block comprises a singlereference terminal which is at a reference potential different from thepotential of the neutral terminal of the source, and in that itcomprises means for permanent maintenance, at a constant sign or zero,of the potential difference between the input terminal and the referenceterminal of the or each commutation block.

According to other features:

the matrix of the or each block comprises at least one level whichcomprises at least one row of commutation cells, which are arranged onthe basis of a single commutation cell for each level of the same row,each commutation cell being composed of two elements which form aswitch, the or each level defining two groups of switches which areconnected in series and the commutation matrix then defining two extremegroups of switches, each commutation cell being associated with acapacitor which is sized in order to maintain, between the homologousterminals of the two switches of each commutation cell, a chargingvoltage which is equal to a fraction of the voltage of the inputalternating voltage source, which voltage fraction decreases as afunction of the row thereof starting from this source, the capacitors ofthe same row being connected in series between the two extreme groups ofswitches;

all of the switches of each commutation cell are unidirectional in termsof voltage and bidirectional in terms of current;

all of the switches of each commutation cell are formed by electroniccomponents which are unidirectional in terms of voltage andunidirectional in terms of current;

all of the switches of each commutation cell are formed by electroniccomponents which are all identical, and in that each switch isconstituted by identical elementary switches which are connected inseries and the number of which is a function of the maximum voltageapplicable between the terminals thereof;

it comprises means for monitoring the control means comprising means forprocessing a reference signal in order to supply at the output aplurality of secondary reference signals, and means for transmittingeach secondary reference signal to all of the control means of thecommutation cells of the same level of all of the matrices of all of theblocks of the device;

the processing means are suitable for supplying a plurality of secondaryreference signals which are functions related by a portion of thereference signal, each secondary reference signal of a level having atall times a value greater than or equal to the value of a secondaryreference signal of a level which is closer to the voltage source;

the monitoring means comprise means for generating a synchronisationsignal in order to supply at the output a plurality of secondarysynchronisation signals, and means for transmitting each secondarysynchronisation signal to all of the control means of the commutationcells of the same row of all of the matrices of all of the blocks of thedevice;

it comprises a single commutation block and can be connected to a singleinput alternating voltage source, the neutral terminal of which isaccessible in order to allow a connection and which is associated with asingle load which forms an output alternating current source, and inthat it further comprises a first capacitor which can be connectedbetween the neutral terminal of the source and an output terminal of theload and a second capacitor which can be connected between the referenceterminal of the commutation block and the output terminal of the load;

it comprises a single commutation block and can be connected to a singleinput alternating voltage source, the neutral terminal of which isaccessible in order to allow a connection and which is associated with asingle load which forms an output alternating current source, and itcomprises a shift block which comprises an input terminal which issuitable for being connected to the neutral terminal of the source, areference terminal which is connected to the reference terminal of thecommutation block and an output terminal which can be connected to theoutput terminal of the load, the shift block allowing the potential ofthe output terminal, which can be connected to an output terminal of theload, to be modified;

it comprises a first commutation block and a second commutation blockand can be connected to a single input alternating voltage source, theneutral terminal of which is accessible in order to allow a connectionand which is associated with a single load which forms an outputalternating current source, the reference terminals of the twocommutation blocks being connected to each other, the first commutationblock being suitable for being connected at the input terminal thereofto the supply terminal of the source, the second commutation block beingsuitable for being connected at the input terminal thereof to theneutral terminal of the source, the device further being suitable forconnecting the load between the output terminals of the two commutationblocks;

the means for permanent maintenance, at a constant sign or zero, of thepotential difference between the input terminal and the referenceterminal comprise inhibiting means which are associated with the or eachcommutation block and which comprise means for evaluating the sign ofthe potential difference between the input terminal and the neutralterminal of the source, which evaluation means are suitable forsupplying at the output a signal for inhibiting the commutation block,and the or each commutation block is suitable for connecting togetherthe input terminal, the reference terminal and the output terminalthereof when the inhibiting signal is received;

the inhibiting means are suitable for supplying the inhibiting signalwhen the potential difference between the input terminal and the neutralterminal of the source is negative, the commutation matrix further beingformed by electronic components which are orientated so that thecommutation block supports only a positive voltage or zero voltage;

the inhibiting means are suitable for supplying the inhibiting signalwhen the potential difference between the input terminal and the neutralterminal of the source is positive, the commutation matrix further beingformed by electronic components which are orientated so that thecommutation block supports only a negative voltage or zero voltage;

it can be connected to at least two input alternating voltage sources,the neutral terminals of which are all connected to each other and whichare associated with the same number of loads which form outputalternating current sources and output terminals of which are also allconnected to each other, and it comprises a plurality of commutationblocks, the reference terminals of the commutation blocks all beingconnected to each other;

the neutral terminals of the sources are accessible in order to allow aconnection, and it comprises a shift block which comprises an inputterminal which is suitable for being connected to the neutral terminals,a reference terminal which is connected to all of the referenceterminals of the commutation blocks and an output terminal which can beconnected to all of the output terminals of the loads which form anoutput alternating current source, the shift block allowing thepotential of the output terminal, which can be connected to the outputterminals of the loads, to be modified;

the means for permanent maintenance, at a constant sign or zero, of thepotential difference between the input terminal and the referenceterminal comprise inhibiting means which are associated with the or eachcommutation block and which comprise means for comparing the potentialdifference between the input terminals and a terminal having a potentialcommon to all of the commutation blocks, such as the neutral terminalsof the sources, the output terminals of the loads or the referenceterminals, which means are suitable for supplying at the output signalsfor inhibiting the commutation blocks, and the or each commutation blockis suitable for connecting together the input terminal, the referenceterminal and the output terminal thereof when the inhibiting signal isreceived;

the inhibiting means are suitable for supplying an inhibiting signalonly to the block whose potential difference between the input terminalsand a terminal having a potential common to all of the commutationblocks, such as the neutral terminals of the sources, the outputterminals of the loads or the reference terminals, is the weakest, thecommutation matrices further being formed by electronic components whichare orientated so that the blocks support only a positive voltage orzero voltage;

the inhibiting means are suitable for supplying an inhibiting signalonly to the block whose potential difference between the input terminalsand a terminal having a potential common to all of the commutationblocks, such as the neutral terminals of the sources, the outputterminals of the loads or the reference terminals, is the greatest, thecommutation matrices further being formed by electronic components whichare orientated so that the blocks support only a negative voltage orzero voltage;

it is suitable for being connected to three input alternating voltagesources which form the three phases of a three-phase electrical energysupply network;

each matrix of each commutation block comprises a single capacitor and asingle commutation cell.

The invention will be better understood from a reading of thedescription below which is given purely by way of example and withreference to the drawings, in which:

FIG. 1 is a schematic block diagram of a converting device according tothe invention;

FIG. 2 is a schematic electrical diagram of a commutation block;

FIGS. 3, 4 and 5 are block diagrams, each illustrating in detail theproduction of a device according to the invention, in the specific caseof connection to a single input alternating voltage source;

FIG. 6 is a block diagram illustrating in detail an energy convertingdevice according to the invention in the specific case of three inputalternating voltage sources;

FIGS. 7 and 8 are schematic electrical diagrams of a commutation matrixused in the invention when it comprises two levels and two rows, furtherillustrating in detail a control assembly of this device;

FIG. 9 is an illustration of the course of the reference signals of thedevice described with reference to FIGS. 6 to 8;

FIG. 10 is an illustration of the course of the control signals of thedevice described with reference to FIGS. 6 to 8;

FIG. 11 is an illustration of the course of the voltage between theinput terminal and the reference terminal of a commutation block of thedevice described with reference to FIGS. 6 to 8;

FIG. 12 is an illustration of the course of the output voltages of thecommutation blocks of the device described with reference to FIGS. 6 to8; and

FIG. 13 is an illustration of the course of the output currents of thecommutation blocks of the device described with reference to FIGS. 6 to8.

FIG. 1 illustrates an energy converting device according to theinvention.

This device is connected to a plurality of input alternating voltagesources 1 ₁ to 1 _(n) which are constituted, for example, by the variousphases of a multi-phase supply network.

The input alternating voltage sources 1 ₁ to 1 _(n) are all out of phaserelative to each other. In this manner, if the system has n inputalternating voltage sources, they are out of phase relative to eachother by $\frac{2\pi}{n}.$

These input alternating voltage sources 1 ₁ to 1 _(n) each comprise asupply terminal 2 ₁ to 2 _(n) and a neutral terminal 3 ₁ to 3 _(n),which neutral terminals 3 _(1 to 3) _(n) can be accessible or not. Theyare associated with loads 4 ₁ to 4 _(n) by means of commutation blocks 6₁ to 6 _(n) which are integrated in the energy converting device. Theloads 4 ₁ to 4 _(n) are bi-polar elements which are constituted, forexample, by resistors in series with inductors, and act as currentsources. They each have an output terminal 5 ₁ to 5 _(n).

Each of the commutation blocks 6 ₁ to 6 _(n) comprises an input terminal7 ₁ to 7 _(n) which is connected to the supply terminal 2 ₁ to 2 _(n) ofthe voltage source 1 ₁ to 1 _(n) which is associated therewith.

Each of the blocks 6 ₁ to 6 _(n) further comprises a single referenceterminal 9 ₁ to 9 _(n) and an output terminal 10 ₁ to 10 _(n). It alsocomprises a commutation matrix 12 ₁ to 12 _(n) and associated inhibitingmeans 13 ₁ to 13 _(n) which are suitable for connecting together theinput terminal 7 _(j), the reference terminal 9 _(j) and the outputterminal 10 _(j), of the block, thereby inhibiting the block inquestion.

When the device comprises at least two input alternating voltage sources1 ₁ to 1 _(n), each associated with a commutation block 6 ₁ to 6 _(n),the neutral terminals 3 ₁ to 3 _(n) of the sources 1 ₁ to 1 _(n) are allconnected together at the same potential.

For example, this potential is the neutral of the supply networkcorresponding to the input alternating voltage sources 1 ₁ to 1 _(n).

Furthermore, the reference terminals 9 ₁ to 9 _(n) of all of thecommutation blocks 6 ₁ to 6 _(n) are connected to each other andconstitute a common reference potential. The output terminals 5 ₁ to 5_(n) of the loads 4 ₁ to 4 _(n) are also all connected to each other atthe same potential.

Finally, the inhibiting means 13 ₁ to 13 _(n) comprise means forcomparing existing voltages between the input terminals 7 ₁ to 7 _(n)and a terminal having a common potential for all of the blocks 6 ₁ to 6_(n), such as the reference terminals 9 ₁ to 9 _(n) the output terminals5 ₁ to 5 _(n) or the neutral terminals 3 ₁ to 3 _(n).

In FIG. 1, as well as in the other Figures, the inhibiting means 13 ₁ to13 _(n) are illustrated delocalised at the commutation blocks 6 ₁ to 6_(n). However, these circuits can also be grouped into a centralinhibiting circuit comprising single comparison means and controllingall of the blocks 6 ₁ to 6 _(n).

When the neutral terminals 3 ₁ to 3 _(n) are accessible, the convertingdevice advantageously comprises a shift block 14 whose architecture isidentical to that of the commutation blocks, but without beingassociated with an input alternating voltage source.

The input terminal 15 is then connected to all of the neutral terminals3 ₁ to 3 _(n) of the sources 1 ₁ to 1 _(n).

The shift block 14 also comprises a reference terminal 16 and an outputterminal 17. It is constituted by a commutation matrix 18 which isidentical to the matrices 12 ₁ to 12 _(n) of the commutation blocks 6 ₁to 6 _(n).

The reference terminal 16 is connected to the reference terminals 9 ₁ to9 _(n) of the commutation blocks 6 ₁ to 6 _(n) and the output terminal17 is connected to the output terminals 5 ₁ to 5 _(n) of the loads 4 ₁to 4 _(n), as is described with reference to FIGS. 2, 7 and 8.

The shift block 14 allows the potential of the output terminals 5 ₁ to 5_(n) of loads 4 ₁ to 4 _(n) to be shifted, as is described withreference to FIGS. 2, 7 and 8.

The converting device is thereby adapted to the type of the loads 4 ₁ to4 _(n).

FIG. 2 illustrates the architecture of a commutation matrix 12 _(j),similar to those used in the invention.

The commutation block 6 _(j) comprises an input terminal 7 _(j), towhich the supply terminal 2 _(j) of an alternating voltage source 1_(j), an output terminal 10 _(j) and a reference terminal 9 _(j) areconnected.

The commutation block 6 _(j) comprises a commutation matrix 12 _(j)which is formed by capacitors 20 _(j,1,1) to 20 _(j,n,p) and commutationcells 22 _(j,1,1) to 22 _(j,n,p).

Each commutation cell 22 _(j,i,k) is constituted by two switches 24_(j,i,k) and 26 _(j,i,k) and is connected, for the monitoring thereof,to control means 28 _(j,i,k) which are specific thereto.

In this device, the switches are unidirectional in terms of voltage andbidirectional in terms of current and the electronic components whichform the switches 24 _(j,i,k) and 26 _(j,i,k) of the commutation cells22 _(j,1,1) to 22 _(j,n,p) are unidirectional in terms of current andvoltage, as is described with reference to FIG. 8.

The capacitors 20 _(j,i,k) and commutation cells 22 _(j,i,k) which formthe matrix 12 _(j) as a whole are ordered in n levels 30 _(j,1) to 30_(j,n) and p rows 32 _(j,1) to 32 _(j,p).

Each matrix 12 _(j) optionally comprises a single level 30 _(j,1,1) anda single row 32 _(j,1,1). In this case, the matrix 12 _(j) isconstituted by a single commutation cell 22 _(j,1,1) and a singlecapacitor 20 _(j,1,1).

The n levels of the matrix 12 _(j) define n+1 groups of switches.

The first group of switches is constituted by the series-connectedcircuit breakers 24 _(j,1,1) to 24 _(j,1,p) of the p commutation cellsof the first level. The (n+1)th group of switches is constituted by theseries-connected switches 26 _(j,n,1) to 26 _(j,n,p) of the pcommutation cells of the nth level. The ith group of switches, with1<i≦n, is constituted by the switches 24 _(j,i,1) to 24 _(j,i,p) of thep commutation cells of the ith level and the switches 26 _(j,i−1,1) to26 _(i,i−1,p) of the p commutation cells of the (i−1)th level,alternately connected in series.

All of the groups of switches are connected at one of the ends thereofto the output terminal 10 _(j) of the commutation block 6 _(j).

The matrix 12 _(j) of the commutation block 6 _(j) further defines twoextreme groups of switches. The first one is connected at one end to theoutput terminal 10 _(j) and at the other end to the reference terminal 9_(j). The (n+1)th is connected at one end to the output terminal 10 _(j)and at the other end to the input terminal 7 _(j).

Between two successive rows 32 _(j,k) and 32 _(j,k+1), n capacitors ofrow k, 20 _(j,1,k) to 20 _(j,n,k), are connected in series on the basisof one per level. In this manner, at the ith level, the capacitor 20_(j,i,k) is connected, on the one hand, to the ith group of switchesand, on the other hand, to the (i+1)th group of switches.

Each capacitor 20 _(j,i,k) is suitable for maintaining between theterminals thereof a charging voltage, being an increasing function ofrow k thereof and representing a fraction of the partial voltage of thevoltage source 1 _(j).

All of the commutation blocks 6 ₁ to 6 _(n) used in a converting deviceaccording to the invention, as well as the shift block 14, areconstituted in the same manner as the commutation block 6 _(j) describedwith reference to FIG. 2.

In the same device, all of the commutation blocks 6 ₁ to 6 _(n) furthercomprise a matrix 12 ₁ to 12 _(n) which comprises the same number oflevels and rows, and therefore the same number of commutation cells andcapacitors.

The operation of such a device will now be explained.

Each of the commutation blocks 6 ₁ to 6 _(n) has two operating modeswhich are imposed by the inhibiting means 13 ₁ to 13 _(n).

In a first operating mode, a commutation block 6 _(j) converts the inputsignal into an output signal of the same type and having the samefrequency.

In this first operating mode, the commutation cells 22 _(j,i,k) of thecommutation blocks 6 ₁ to 6 _(n) are controlled so as to maintain thetwo switches of each cell in opposite states.

The voltage between the input terminal 7 _(j) and the reference terminal9 _(j) therefore has a constant sign. The sign thereof is determined bythe orientation of the components in the matrix 12 _(j).

For example, a given orientation of the components, described below withreference to FIG. 8, leads to a potential difference between the inputterminal 7 _(j) and the reference terminal 9 _(j) that is constantlypositive.

In this case, when the comparison means of the inhibiting means 13 _(j)detect that the voltage between the input terminal 7 _(j) and a terminalhaving a potential common to all of the blocks 6 ₁ to 6 _(n), such asthe neutral terminal 3 ₁ to 3 _(n), the output terminal 5 ₁ to 5 _(n) orthe reference terminal 9 ₁ to 9 _(n), is less than the voltages betweenthe input terminals of all of the other blocks of the system, and thesame terminal having a common potential, the inhibiting means 13 _(j)supply an inhibiting signal to the commutation block 6 _(j).

The commutation block then switches into a second operating mode, knownas the “commutation block inhibition” mode, all of the switches formingthe commutation cells of a commutation block 6 _(j) are closed, therebyshort-circuiting the input terminal 7 _(j), the reference terminal 9_(j) and the output terminal 10 _(j) of the commutation block 6 _(j).

When the orientation of the components imposes a voltage between theterminals 7 _(j) and 9 _(j) that is constantly negative during thecommutation phases, the inhibition criterion is inverted.

Owing to the inhibiting conditions of a commutation block which aredescribed above, there can be only one commutation block functioning ata time in the inhibition mode among all of the commutation blocks 6 ₁ to6 _(n) of the converting device.

If the device comprises a shift block, it functions in the same manneras a non-inhibited commutation block.

The input alternating voltage sources 1 ₁ to 1 _(n) being out of phaserelative to each other, each of the commutation blocks 6 ₁ to 6 _(n)switches to the inhibited mode for a period of $\frac{2\pi}{n}.$

In such a device, placing all of the reference terminals 9 ₁ to 9 _(n)and all of the neutral terminals 3 ₁ to 3 _(n) at the same potential,the inhibiting periods controlled by the inhibiting means and theorientation of the components ensure that the voltage between the inputterminal 7 ₁ to 7 _(n) and the reference terminal 9 ₁ to 9 _(n) of eachof the commutation blocks is maintained at a constant sign or zero.

These voltages, referred to as Vb₁ to Vb_(n), respectively, remaindirectly linked with the source voltages 1 ₁ to 1 _(n) referred to as V1₁ to V1 _(n).

It will be appreciated that, at all times, the relationship Vb₁-Vb₃=V1₁-V1 ₃ is verified. This relationship is verified for all of the blocksby circular permutation.

Similarly, the combined output voltages of the blocks referred to as V10₁-V10 _(j) are also sinusoidal and generate in the loads 4 ₁ to 4 _(n)sinusoidal currents which have the same frequency as the inputalternating voltage sources 1 ₁ to 1 _(n) and which are out of phaserelative to each other by $\frac{2\pi}{n}.$

In FIG. 3, the architecture of a device according to the invention whichis connected to a single input alternating voltage source 1 is defined.

The device is connected to a load 4 which is associated with an inputalternating voltage source 1, the neutral terminal 3 of which isaccessible and comprises a commutation block 6.

The commutation block 6 comprises an input terminal 7 which is connectedto the supply terminal 2 of the input alternating voltage source 1. Itfurther comprises a reference terminal 9, an output terminal 10 which isconnected to the load 4 and a commutation matrix 12 which is associatedwith inhibiting means 13.

In this configuration, the device further comprises a first capacitor 20which is connected between the neutral terminal 3 of the source 1 andthe output terminal 5 of the load 4 and a second capacitor 22 which isconnected between the output terminal 5 of the load 4 and the referenceterminal 9 of the commutation block 6.

In this manner, a circuit is obtained which is suitable for constantlymaintaining a potential difference between the reference point 9 of thecommutation block 6 and the neutral terminal 3 of the input alternatingvoltage source 1.

In this configuration, the inhibiting means 13 of the commutation block6 further comprise means for evaluating the sign of the potentialdifference between the input terminal 7 and the neutral terminal 3,which corresponds to the potential difference at the source terminals 1.

When this voltage has a given sign, that is, for example, positive orzero, the block 6 functions as a commutation block. If this voltage hasthe opposite sign, negative in the example, the inhibiting means 13control the commutation matrix 12 so that all of the switches areclosed, thereby short-circuiting the input terminal 7, the referenceterminal 9 and the output terminal 10, the block 6 then switches to theinhibited mode.

In order to reconstitute the integrity of a sinusoidal signal, thecircuit must advantageously comprise means for shifting the signal ofthe input alternating voltage source 1 so that the input voltage isalways positive or zero.

FIG. 4 illustrates the case of a device according to the invention whichis connected to a single input alternating voltage source 2, the neutralterminal 3 of which is accessible, and which device comprises a shiftblock 14.

As has been described with reference to FIG. 3, the device is connectedto the input alternating voltage source 1, which is associated with theload 4 acting as a source of output current, and comprises thecommutation block 6.

The commutation block 6 comprises the matrix 12 which is associated withthe inhibiting means 13.

The device further comprises a shift block 14 which has an inputterminal 15 which is connected to the neutral terminal 3 of the source1, an output terminal 17 which is connected to the output terminal 5 ofthe load 4 and a reference terminal 16 which is connected to thereference terminal 9 of the commutation block 6.

The shift block 14 allows the potential of the output terminal 5 of theload 4 to be modified, as is described with reference to FIGS. 2, 7 and8.

FIG. 5 illustrates a variant of the case of a device according to theinvention which is connected to a single input alternating voltagesource 1, the neutral terminal 3 of which is accessible.

When the device is connected to a single input alternating voltagesource 1 whose supply terminal 2 and neutral terminal 3 are accessible,this input alternating source 1 can be considered to be formed by twoalternating sources 11 and 12 in phase-opposition.

The device therefore comprises two commutation blocks 6 ₁ and 6 ₂ whichare connected to the two virtual sources 1 ₁ and 1 ₂ in conventionalmanner, as has been described with reference to FIG. 1, the neutralterminal 3 acting as the supply terminal 2 ₂.

The commutation block 6 ₁ is associated with a load 4 ₁ and thecommutation block 6 ₂ is associated with a load 4 ₂. These two loads 4 ₁and 4 ₂ are connected to each other at the output terminals 5 ₁ and 5 ₂thereof.

Optionally, the two loads 4 ₁ and 4 ₂ can be replaced with a single load4 which is connected between the output points 10 ₁ and 10 ₂ of thecommutation blocks 6 ₁ and 6 ₂.

Such a device functions in the same manner as the general devicedescribed with reference to FIG. 1.

In such a physical configuration, however, it is not possible to connecta shift block.

The operation of a device according to the invention is described on thebasis of the specific case described with reference to FIGS. 6 to 8.

FIG. 6 illustrates a converting device according to the invention in thespecific case in-which it is connected to three input alternatingvoltage sources 1 ₁, 1 ₂ and 1 ₃ which are associated with three loads 4₁, 4 ₂ and 4 ₃ by means of commutation blocks 6 ₁, 6 ₂ and 6 ₃.

The three input alternating voltage sources 1 ₁, 1 ₂ and 1 ₃ supply thesame sinusoidal alternating signal of frequency f and are phase-shiftedrelative to each other by temporal spacing of $\frac{1}{3f}.$They each have a supply terminal 2 ₁, 2 ₂ and 2 ₃ and a neutral terminal3 ₁, 3 ₂ and 3 ₃ which can be accessible or not.

For example, in the case of a three-phase supply network, each of theinput alternating voltage sources represents a phase of the network.

Each commutation block 6 ₁, 6 ₂ and 6 ₃ comprises an input terminal 7 ₁,7 ₂ and 7 ₃, a reference terminal 9 ₁, 9 ₂ and 9 ₃ and an outputterminal 10 ₁, 10 ₂ and 10 ₃. The input terminals 7 ₁, 7 ₂ and 7 ₃ areconnected to the supply terminals 2 ₁, 2 ₂ and 2 ₃ and are indicated bythe same references 7 ₁, 7 ₂ and 7 ₃.

They comprise commutation matrices 12 ₁, 12 ₂ and 12 ₃ which areassociated with inhibiting means 13 ₁, 13 ₂ and 13 ₃, respectively.

In a specific case, each commutation matrix 12 ₁, 12 ₂ and 12 ₃comprises only one level and only one row and therefore only onecommutation cell which is associated with a single capacitor.

As has been defined with reference to FIG. 1, the neutral terminals 3 ₁,3 ₂ and 3 ₃ are all connected to each other and define a neutral whichis common to the three input alternating voltage sources 1 ₁, 1 ₂ and 1₃.

The reference terminals 9 ₁, 9 ₂ and 9 ₃ are connected to each other, asare the output terminals 5 ₁, 5 ₂ and 5 ₃ of the loads 4 ₁, 4 ₂ and 4 ₃.

The details of the commutation block 6 ₁ and the control system thereofare described with reference to FIGS. 7 and 8.

The matrix 12 ₁ of the block 6 ₁ comprises two levels 30 _(1,1) and 30_(1,2) and two rows 32 _(1,1) and 32 _(1,2). Therefore, it comprisesfour commutation cells 22 _(1,1,1), 22 _(1,1,2), 22 _(1,2,1) and 22_(1,2,2) which are associated with the four capacitors 20 _(1,1,1), 20_(1,1,2), 20 _(1,2,1) and 20 _(1,2,2) and which are controlled by fourcontrol devices 28 _(1,1,1), 28 _(1,1,2), 28 _(1,2,1) and 28 _(1,2,2),respectively.

The control system is constituted by a synchronisation module 34 whichcomprises means 36 for generating symmetrical, alternating, triangularsignals of frequency F as well as a delay circuit 38, which produce twosignals Sd₁ and Sd₂ which are phase-shifted by a temporal spacing of$\frac{1}{2F}$and which supply the control devices 28 _(1,1,1), 28 _(1,2,1) of thefirst row and 28 _(1,1,2), 28 _(1,2,2) of the second row, respectively.

Of course, if each commutation matrix comprises p rows, the triangularsignals which are emitted by the synchronisation module 34 are allphase-shifted by a temporal spacing of $\frac{1}{pF}.$

These synchronisation signals are used by all of the commutation blocksof the device.

In the embodiment described here, frequency F is clearly greater thanfrequency f of the alternating voltage sources 1 ₁, 1 ₂ and 1 ₃ and isselected to represent more precisely a multiple of f for the sake ofsimplicity.

The device also comprises a monitoring signal generator 40 whichsupplies a continuous reference signal Sr which varies between 0 and 1and which corresponds to the adjustment of the quantity of energy to betransferred between the input alternating voltage source 6 ₁ and thecurrent source 4 ₁.

This reference signal Sr is processed at the output of the monitoringgenerator 40 by two processing modules 42 and 44 of the first and secondlevels in order to provide at the output two secondary reference signalsSr₁ and Sr₂, respectively. These two signals Sr₁ and Sr₂ supply thecontrol devices 28 _(1,1,1), 28 _(1,1,2) of the first level and 28_(1,2,1), 28 _(1,2,2) of the second level, respectively.

These secondary control signals are used by all of the commutationblocks of the device.

The four control devices 28 _(1,1,1) to 28 _(1,2,2) are synchronised andsupply control signals at a frequency F, which signals are suitable forensuring, outside the inhibiting periods of the block 6 ₁, that the twoswitches of each cell are commutated to opposite states.

Each control device 28 _(1,1,1) to 28 _(1,2,2) comprises, for example, acomparator whose logic state at the output is the result of thecomparison of three signals, one of which is output by thesynchronisation module 34, another by the monitoring generator 40 and athird by the inhibiting means 13 ₁.

Therefore, the control device 27 _(1,i,k) supplies at the output acontrol signal Sc_(1,i,k) whose value determines the state of thecommutation cell 22 _(1,i,k).

This control signal Sc_(1,i,k) must allow the three states of acommutation cell to be differentiated, that is to say, the two states ofopposite commutation of the switches and the inhibiting state, in whichthe two switches are closed.

An example of such a control system is described with reference to FIG.8.

In the embodiment described, it will be noted that the switches of theextreme groups can support a voltage double that supported by theswitches of the intermediate group.

Advantageously, the switches 24 _(1,1,1), 24 _(1,2,1), 26 _(1,1,2) and26 _(1,2,2) of the extreme groups are formed by two identical elementaryswitches 50 which are arranged in series and which are controlled inorder to be in the same state at all times. Each elementary switch 50 isformed by a transistor 52 which is arranged with a diode 54 in ananti-parallel state. In this manner, all of the electronic componentsforming the switches of a commutation block are identical.

Furthermore, all of the electronic components forming the elementaryswitches 50 of all of the commutation blocks of a device according tothe invention are unidirectional in terms of current and voltage. In theexample described with reference to FIG. 8, the voltage between theinput terminal 7 ₁ and the reference terminal 9 ₁ is always positive orzero.

When all of the polarised electronic components of the device areinverted, this voltage is negative or zero.

A variant of the control system will now be explained in detail withregard to the switches of a commutation cell, and more precisely thecommutation cell 22 _(1,2,2).

This cell comprises a first switch 24 _(1,2,2) which is formed by asingle elementary switch 50 and a second switch 26 _(1,2,2) which isformed by two elementary switches 50. The cell is controlled by thecontrol device 28 _(1,2,2).

This control device 28 _(1,2,2) generates a control signal Sc_(1,2,2)and is connected at the output directly to a first logic gate OR and, bymeans of an inverter, to a second logic gate OR.

The two gates OR are further connected to the inhibiting means 13 ₁ andreceive signal In₁.

The first gate OR is connected at the output to the two elementaryswitches which constitute the switch 26 _(1,2,2) in order to supply thecontrol signal Sc26 _(1,2,2) which is obtained for an OR logic operationbetween the signals Sc_(1,2,2) and In₁.

The second gate OR is connected at the output to the switch 24 _(1,2,2)in order to supply the control signal Sc24 _(1,2,2) which is obtained byan OR logic operation between the signals Sc_(1,2,2) and In₁.

Therefore, it will be appreciated that, when the inhibiting signal In₁equals zero, the control signals Sc24 _(1,2,2) and Sc26 _(1,2,2) arecomplementary, which allows commutation to opposite states to be ensuredfor the two switches which form the cell 22 _(1,2,2).

When the signal In₁ equals 1, the two control signals Sc24 _(1,2,2) andSc26 _(1,2,2) equal 1, which corresponds to the closing of the switches24 _(1,2,2) and 26 _(1,2,2). The cell 22 _(1,2,2) is then inhibited.

The other cells of the device are controlled similarly.

In another example, the control signals are constituted by a numericalcontrol encoded in two bits.

In this manner, when the inhibiting signal In₁ equals 0, the controlsignal Sc_(1,i,k) equals 01 or 00. In the case in which it is equal to01, the switch 24 _(1,i,k) of the commutation cell 22 _(1,i,k) is closedand the switch 26 _(1,i,k) of the same cell is open. Conversely, whenthe control signal Sc_(1,i,k) is equal to 00, the switch 24 _(1,i,k) ofthe commutation cell 22 _(1,i,k) is open and the switch 26 _(1,i,k) ofthe same cell is closed.

Finally, if the commutation block 6 ₁ is inhibited, inhibiting signalIn₁ is equal to 1, signal Sc_(1,i,k) is equal to 11 or 10, and all ofthe switches of the commutation cells 22 _(1,1,1) to 22 _(1,2,2) areclosed.

When the device comprises a shift block, it is controlled in the samemanner as a commutation block in the absence of the inhibiting signal.Therefore, all of the switches are controlled in opposed commutations.

The simultaneous control of the two switches of the same cell will notbe further described below, being considered to be known in the priorart.

As will be appreciated with reference to FIG. 9, signal Sr₁ intended forthe control devices of the first level 30 _(1,1) is equal to 2×Srbetween 0 and ½ and is fixed at 1 between ½ and 1. Signal Sr₂ intendedfor the control devices of the second level 30 _(1,2) is equal to 0 upto ½, then 2× Sr between ½ and 1.

When the matrices 12 ₁ to 12 ₃ of the commutation blocks 6 ₁ to 6 ₃comprise three levels, it is advantageous to determine three secondarycontrol signals. The first is equal to 3× Sr between 0 and ⅓, then beingfixed at 1, the second is equal to 0 before ⅓, 3× Sr between ⅓ and ⅔ and1 after ⅔, and the third is equal to 0 before ⅔ and 3× Sr between ⅔and 1. Generally, a device which comprises n level(s) has n signals Sr₁to Sr_(n).

For example, in the device described with reference to FIG. 6 to 9, ifsignal Sr is equal to 0.25, signal Sr₁ equals 0.5 and signal Sr₂ iszero.

FIG. 10 illustrates, on the one hand, the course of the three signalsSr₁, Sd₁ and In₁ which are provided at the input of the control device28 _(1,1,1) and, on the other hand, the course of the control signalSc26 _(1,1,1) which is provided by the control device 28 _(1,1,1) to theswitch 26 _(1,1,1) as a function of the signals received at the input.

The control signal Sc24 _(1,1,1) directed to the switch 24 _(1,1,1) isnot illustrated.

Signal Sd₁ is a triangular signal having an amplitude which variesbetween 0 and 1 and a frequency F which here is 20 f.

For the first row of the first level, when the inhibiting signal In₁ iszero, signal Sc26 _(1,1,1) is a signal of rectangular wave form having azero value when the relationship Sd₁>Sr₁ is verified and which has avalue of one when the relationship Sd₁<Sr₁ is verified, as isillustrated with reference to FIG. 10.

This signal and signal Sc24 _(1,1,1) are complementary and produce thecommutation to opposite states of the switches of the commutation cell22 _(1,1,1).

When signal In₁ is equal to 1, signals Sc24 _(1,1,1) and Sc26 _(1,1,1)are fixed at 1 and all of the switches of the commutation cell 22_(1,1,1) are closed.

All of the cells of the commutation matrix receive the same inhibitingsignal In₁, and therefore all of the switches are closed. The block isthen in the inhibiting mode.

For the first row of the second level, in the example selected withSr=0.25, signal Sr₂ is zero. In fact, when In₁ is zero, Sr₂ being lessthan Sd₁, signal Sc_(1,2,1) is equal to zero. The commutation cell 22_(1,2,1) is in a fixed state, the switch 26 _(1,2,1) being open and theswitch 24 _(1,2,1) being closed.

When In₁ is equal to 1, the commutation block 6 is inhibited, signalsSc24 _(1,2,1) and Sc26 _(1,2,1) are fixed at 1 and all of the switchesare closed.

For the second row of the device, signal Sd₂ is a triangular signalwhich has an amplitude which varies between 0 and 1 and a frequency Fand which is phase-shifted by temporal spacing of $\frac{1}{2F}$relative to signal Sd₁. Signals Sc_(1,1,2) and Sc_(1,2,2) are thensignals of rectangular wave form which are phase-shifted by temporalspacing of $\frac{1}{2F}$relative to signals Sc_(1,1,1) and Sc_(1,2,1).

Furthermore, inhibiting signal In₁ is common to all of the cells of theblock. Consequently, the various rows of the same level behave in asimilar manner and have temporal spacing of $\frac{1}{2F}.$

FIG. 11 illustrates the input voltage of one of the commutation blocksof the device described with reference to FIG. 6 to 10.

Voltage Vb₁ corresponds to the potential difference between the inputterminal 7 ₁ of the commutation block 6 ₁ and the reference terminal 9₁.

It will be appreciated that, although the voltage source 1 ₁ associatedwith the block 6 ₁ is a sinusoidal alternating source, voltage Vb₁ has aparticular shape because of the variations of the potential of thereference terminal 9 ₁ and the inhibiting period of the commutationblock 6 ₁.

It has a positive portion with a double curve over a period of ⅔ f and azero portion over a period of ⅓ f corresponding to the inhibiting periodof the block 6 ₁.

Voltages Vb₂ and Vb₃ have the same shape as voltage Vb₁, beingphase-shifted relative to each other by one-third of a period.

Each of the commutation blocks 6 ₁, 6 ₂ and 6 ₃ is inhibited forone-third of the period corresponding to frequency f of the inputalternating voltage sources 1 ₁, 1 ₂ and 1 ₃.

The three voltage sources 1 ₁, 1 ₂ and 1 ₃ are further phase-shiftedrelative to each other by one-third of a period.

The output voltages of the commutation blocks 6 ₁, 6 ₂ and 6 ₃ areillustrated with reference to FIG. 12.

These output voltages Vs₁, Vs₂ and Vs₃ correspond to the potentialdifference between the output terminals 10 ₁, 10 ₂ and 10 ₃ of thecommutation blocks 6 ₁, 6 ₂ and 6 ₃ and the reference terminals 9 ₁, 9 ₂and 9 ₃ thereof.

They have an envelope corresponding to the general shape of inputvoltages Vb₁, Vb₂ and Vb₃ which are modulated to frequency F of thecontrol means.

The illustration in FIG. 12 is symbolic and the ratio 20 betweenfrequencies f and F has not been complied with.

The charging currents which appear in the loads 4 ₁, 4 ₂ and 4 ₃ areillustrated with reference to FIG. 13.

It will be appreciated that the charging currents I4 ₁, I4 ₂ and I4 ₃imposed by the combined voltages Vs₁-Vs₂, Vs₂-Vs₃ and Vs₃-Vs₁ aresinusoidal and have the same frequency f as the input alternatingvoltage sources 1 ₁, 1 ₂ and 1 ₃.

The strength of these currents is fixed in a continuous manner bycontrol signal Sr being determined.

It will clearly be appreciated that a device for converting electricalenergy according to the invention has the advantage, owing to the factthat the input voltage of the commutation blocks always has the samesign or is zero, of being able to use electronic components which arecheaper and of smaller dimensions than existing devices.

Furthermore, the electronic components used in the invention aresubjected to stresses in terms of voltage which are less great thanthose of existing devices.

Therefore, such a device can carry out a conversion of electrical energyof average power or high power between one or more input alternatingvoltage sources and one or more alternating current sources, usinglow-cost elements and with adjustment which is rapid, continuous andreliable.

Furthermore, conventional filters are arranged at each of the inputalternating voltage sources and at each of the output current sources.

1. Device for reversibly converting electrical energy, which device canbe connected between at least one input alternating voltage source (1 ₁to 1 _(n)) and at least one load (4 ₁ to 4 _(n)) which forms an outputalternating current source (4 ₁ to 4 _(n)), each input alternatingvoltage source (1 ₁ to 1 _(n)) having a supply terminal (2 ₁ to 2 _(n))and a neutral terminal (3 ₁ to 3 _(n)), the device comprising at leastone commutation block (6 ₁ to 6 _(n)) which is suitable for beingassociated with an output alternating current source (4 ₁ to 4 _(n)) andwhich comprises an input terminal (7 ₁ to 7 _(n)), to which the supplyterminal (2 ₁ to 2 _(n)) of the input alternating voltage source (1 ₁ to1 _(n)) can be connected, at least one reference terminal (9 ₁ to 9_(n)) and an output terminal (10 ₁ to 10 _(n)), to which the load (4 ₁to 4 _(n)) which forms the output alternating current source can beconnected, the block (6 ₁ to 6 _(n)) also comprising a commutationmatrix (12 ₁ to 12 _(n)) which is formed by capacitors (20 _(j,i,k)) andcommutation cells (22 _(j,i,k)), which cells are controlled individuallyby means (28 _(j,i,k)) for controlling the operation thereof,characterised in that the or each commutation block (6 ₁ to 6 _(n))comprises a single reference terminal (9 ₁ to 9 _(n)) which is at areference potential different from the potential of the neutral terminal(3 ₁ to 3 _(n)) of the source (1 ₁ to 1 _(n)), and in that it comprisesmeans (13 ₁ to 13 _(n), 50) for permanent maintenance, at a constantsign or zero, of the potential difference between the input terminal (7₁ to 7 _(n)) and the reference terminal (9 ₁ to 9 _(n)) of the or eachcommutation block (6 ₁ to 6 _(n)).
 2. Converting device according toclaim 1, characterised in that the matrix (12 ₁ to 12 _(n)) of the oreach block (6 ₁ to 6 _(n)) comprises at least one level (30 _(j,1) to 30_(j,n)) which comprises at least one row (32 _(j,1) to 32 _(j,p)) ofcommutation cells (22 _(j,i,k)), which are arranged on the basis of asingle commutation cell (22 _(j,i,k)) for each level (32 _(j,1) to 32_(j,p)) of the same row (30 _(j,1) to 30 _(j,n)) each commutation cell(22 _(j,i,k)) being composed of two elements which form a switch (24_(j,i,k), 26 _(j,i,k)), the or each level (30 _(j,1) to 30 _(j,n))defining two groups of switches which are connected in series and thecommutation matrix (12 ₁ to 12 _(n)) then defining two extreme groups ofswitches, each commutation cell (22 _(j,i,k)) being associated with acapacitor (20 _(j,1,k)) which is sized in order to maintain, between thehomologous terminals of the two switches (24 _(j,i,k), 26 _(j,i,k)) ofeach commutation cell (22 _(j,i,k)), a charging voltage which is equalto a fraction of the voltage of the input alternating voltage source (1₁ to 1 _(n)), which voltage fraction decreases as a function of the rowthereof starting from this source, the capacitors (20 _(j,i,k)) of thesame row (32 _(j,1) to 32 _(j,p)) being connected in series between thetwo extreme groups of switches.
 3. Device according to claim 2,characterised in that all of the switches (24 _(j,i,k), 26 _(j,i,k)) ofeach commutation cell (22 _(j,i,k)) are unidirectional in terms ofvoltage and bidirectional in terms of current.
 4. Device according toclaim 3, characterised in that all of the switches (24 _(j,i,k), 26_(j,i,k)) of each commutation cell (22 _(j,i,k)) are formed byelectronic components (52, 54) which are unidirectional in terms ofvoltage and unidirectional in terms of current.
 5. Device according toclaim 2, characterised in that all of the switches (24 _(j,i,k), 26_(j,i,k)) of each commutation cell (22 _(j,i,k)) are formed byelectronic components (52, 54) which are all identical, and in that eachswitch is constituted by identical elementary switches (50) which areconnected in series and the number of which is a function of the maximumvoltage applicable between the terminals thereof.
 6. Device according toclaim 2, characterised in that it comprises means (34, 40, 42, 44) formonitoring the control means (28 _(j,i,k)) comprising means (42, 44) forprocessing a reference signal (Sr) in order to supply at the output aplurality of secondary reference signals (Sr₁ to Sr_(n)), and means fortransmitting each secondary reference signal to all of the control means(28 _(j,i,k)) of the commutation cells of the same level of all of thematrices (12 ₁ to 12 _(n)) of all of the blocks (6 ₁ to 6 _(n)) of thedevice.
 7. Device according to claim 6, characterised in that theprocessing means (42, 44) are suitable for supplying a plurality ofsecondary reference signals (Sr₁ to Sr_(n)) which are functions relatedby a portion of the reference signal (Sr), each secondary referencesignal (Sr₁ to Sr_(n)) of a level (30 _(j,k)) having at all times avalue greater than or equal to the value of a secondary reference signalof a level which is closer to the voltage source (1 ₁ to 1 _(n)). 8.Device according to claim 6, characterised in that the monitoring means(34, 40, 42, 44) comprise means for generating a synchronisation signal(34) in order to supply at the output a plurality of secondarysynchronisation signals (Sd₁ to Sd_(p)), and means for transmitting eachsecondary synchronisation signal (Sd₁ to Sd_(p)) to all of the controlmeans (28 _(j,i,k)) of the commutation cells of the same row of all ofthe matrices (12 ₁ to 12 _(n)) of all of the blocks (6 ₁ to 6 _(n)) ofthe device.
 9. Device according to claim 1, characterised in that itcomprises a single commutation block (6) and can be connected to asingle input alternating voltage source (1), the neutral terminal (3) ofwhich is accessible in order to allow a connection and which isassociated with a single load (4) which forms an output alternatingcurrent source, and in that it further comprises a first capacitor (20)which can be connected between the neutral terminal (3) of the source(1) and an output terminal (5) of the load (4) and a second capacitor(22) which can be connected between the reference terminal (9) of thecommutation block (6) and the output terminal (5) of the load (4). 10.Device according to claim 9, characterised in that the means forpermanent maintenance, at a constant sign or zero, of the potentialdifference between the input terminal (7; 7 ₁, 7 ₂) and the referenceterminal (9; 9 ₁, 9 ₂) comprise inhibiting means (13; 13 ₁, 13 ₂) whichare associated with the or each commutation block (6; 6 ₁, 6 ₂) andwhich comprise means for evaluating the sign of the potential differencebetween the input terminal (7) and the neutral terminal (3) of thesource (1), which evaluation means are suitable for supplying at theoutput a signal for inhibiting the commutation block (6), and in thatthe or each commutation block (6; 6 ₁, 6 ₂) is suitable for connectingtogether the input terminal (7; 7 ₁, 7 ₂), the reference terminal (9; 9₁, 9 ₂) and the output terminal (10; 10 ₁, 10 ₂) thereof when theinhibiting signal is received.
 11. Device according to claim 10,characterised in that the inhibiting means (13) are suitable forsupplying the inhibiting signal when the potential difference betweenthe input terminal (7) and the neutral terminal (3) of the source (1) isnegative, the commutation matrix (12) further being formed by electroniccomponents (52, 54) which are orientated so that the commutation blocksupports only a positive voltage or zero voltage.
 12. Device accordingto claim 10, characterised in that the inhibiting means (13) aresuitable for supplying the inhibiting signal when the potentialdifference between the input terminal (7) and the neutral terminal (3)of the source (1) is positive, the commutation matrix (12) further beingformed by electronic components (52, 54) which are orientated so thatthe commutation block supports only a negative voltage or zero voltage.13. Device according to claim 1, characterised in that it comprises asingle commutation block (6) and can be connected to a single inputalternating voltage source (1), the neutral terminal (3) of which isaccessible in order to allow a connection and which is associated with asingle load (4) which forms an output alternating current source, and inthat it comprises a shift block (14) which comprises an input terminal(15) which is suitable for being connected to the neutral terminal (3)of the source (1), a reference terminal (16) which is connected to thereference terminal (9) of the commutation block (6) and an outputterminal (17) which can be connected to the output terminal (5) of theload (4), the shift block (14) allowing the potential of the outputterminal (17), which can be connected to an output terminal (5) of theload (4), to be modified.
 14. Device according to claim 1, characterisedin that it comprises a first commutation block (6 ₁) and a secondcommutation block (6 ₂) and can be connected to a single inputalternating voltage source (1), the neutral terminal (3) of which isaccessible in order to allow a connection and which is associated with asingle load (4) which forms an output alternating current source, thereference terminals of the two commutation blocks (6 ₁, 6 ₂) beingconnected to each other, the first commutation block (6 ₁) beingsuitable for being connected at the input terminal (7 ₁) thereof to thesupply terminal (2) of the source (1), the second commutation block (6₂) being suitable for being connected at the input terminal (7 ₂)thereof to the neutral terminal (3) of the source (1), the devicefurther being suitable for connecting the load (4) between the outputterminals (10 ₁, 10 ₂) of the two commutation blocks.
 15. Deviceaccording to claim 1, characterised in that it can be connected to atleast two input alternating voltage sources (1 ₁ to 1 _(n)), the neutralterminals (3 ₁ to 3 _(n)) of which are all connected to each other andwhich are associated with the same number of loads (4 ₁ to 4 _(n)) whichform output alternating current sources and output terminals (5 ₁ to 5_(n)) of which are also all connected to each other, and in that itcomprises a plurality of commutation blocks (6 ₁ to 6 _(n)), thereference terminals (9 ₁ to 9 _(n)) of the commutation blocks (6 ₁ to 6_(n)) all being connected to each other.
 16. Device according to claim15, characterised in that the neutral terminals (3 ₁ to 3 _(n)) of thesources (1 ₁ to 1 _(n)) are accessible in order to allow a connection,and in that it comprises a shift block (14) which comprises an inputterminal (15) which is suitable for being connected to the neutralterminals (3 ₁ to 3 _(n)), a reference terminal (16) which is connectedto all of the reference terminals (9 ₁ to 9 _(n)) of the commutationblocks (6 ₁ to 6 _(n)) and an output terminal (17) which can beconnected to all of the output terminals (5 ₁ to 5 _(n)) of the loads (4₁ to 4 _(n)) which form an output alternating current source, the shiftblock (14) allowing the potential of the output terminal (17), which canbe connected to the output terminals (5 ₁ to 5 _(n)) of the loads (4 ₁to 4 _(n)), to be modified.
 17. Device according to claim 15,characterised in that the means for permanent maintenance, at a constantsign or zero, of the potential difference between the input terminal (7₁ to 7 _(n)) and the reference terminal (9 ₁ to 9 _(n)) compriseinhibiting means (13 ₁ to 13 _(n)) which are associated with the or eachcommutation block (6 ₁ to 6 _(n)) and which comprise means for comparingthe potential difference between the input terminals (7 ₁ to 7 _(n)) anda terminal having a potential common to all of the commutation blocks (6₁ to 6 _(n)), such as the neutral terminals (3 ₁ to 3 _(n)) of thesources (1 ₁ to 1 _(n)), the output terminals (5 ₁ to 5 _(n)) of theloads (4 ₁ to 4 _(n)) or the reference terminals (9 ₁ to 9 _(n)), whichmeans are suitable for supplying at the output signals for inhibitingthe commutation blocks (6 ₁ to 6 _(n)); and in that the or eachcommutation block (6 ₁ to 6 _(n)) is suitable for connecting togetherthe input terminal (7 ₁ to 7 _(n)), the reference terminal (9 ₁ to 9_(n)) and the output terminal (10 ₁ to 10 _(n)) thereof when theinhibiting signal is received.
 18. Device according to claim 17,characterised in that the inhibiting means (13 ₁ to 13 _(n)) aresuitable for supplying an inhibiting signal only to the block whosepotential difference between the input terminals (7 ₁ to 7 _(n)) and aterminal having a potential common to all of the commutation blocks (6 ₁to 6 _(n)), such as the neutral terminals (3 ₁ to 3 _(n)) of the sources(1 ₁ to 1 _(n)), the output terminals (5 ₁ to 5 _(n)) of the loads (4 ₁to 4 _(n)) or the reference terminals (9 ₁ to 9 _(n)), is the weakest,the commutation matrices (12 ₁ to 12 _(n)) further being formed byelectronic components (52, 54) which are orientated so that the blocks(6 ₁ to 6 _(n)) support only a positive voltage or zero voltage. 19.Device according to claim 18, characterised in that the inhibiting means(13 ₁ to 13 _(n)) are suitable for supplying an inhibiting signal onlyto the block whose potential difference between the input terminals (7 ₁to 7 _(n)) and a terminal having a potential common to all of thecommutation blocks (6 ₁ to 6 _(n)), such as the neutral terminals (3 ₁to 3 _(n)) of the sources (1 ₁ to 1 _(n)), the output terminals (5 ₁ to5 _(n)) of the loads (4 ₁ to 4 _(n)) or the reference terminals (9 ₁ to9 _(n)), is the greatest, the commutation matrices (12 ₁ to 12 _(n))further being formed by electronic components (52, 54) which areorientated so that the blocks (6 ₁ to 6 _(n)) support only a negativevoltage or zero voltage.
 20. Device according to claim 1, characterisedin that it is suitable for being connected to three input alternatingvoltage sources (1 ₁ to 1 ₃) which form the three phases of athree-phase electrical energy supply network.
 21. Device according toclaim 20, characterised in that each matrix (12 ₁, 12 ₂ and 12 ₃) ofeach commutation block (6 ₁, 6 ₂, 6 ₃) comprises a single capacitor (20_(j,i,k)) and a single commutation cell (2 _(j,i,k)).